Unsupported Instructions

The following instructions have not been implemented yet (you will get an error):

  • RV32I Load byte instructions
  • RV32I Store byte instructions
  • RV32I Branch instructions
  • RV32A Atomic extension instructions
  • RV32C Compressed extension instructions
  • RV32F/D floating-point extension instructions
  • RV64I instructions
1
ISA:RV32I
Lines:1
Ready

R-type

R-type
add rd, rs1, rs2
# Description
rd = rs1 + rs2
R-type
sub rd, rs1, rs2
# Description
rd = rs1 - rs2
R-type
xor rd, rs1, rs2
# Description
rd = rs1 ^ rs2
R-type
or rd, rs1, rs2
# Description
rd = rs1 | rs2
R-type
and rd, rs1, rs2
# Description
rd = rs1 & rs2
R-type
sll rd, rs1, rs2
# Description
rd = rs1 << rs2
R-type
srl rd, rs1, rs2
# Description
rd = rs1 >> rs2
R-type
sra rd, rs1, rs2
# Description
rd = rs1 >> rs2
R-type
slt rd, rs1, rs2
# Description
rd = (rs1 < rs2)?1:0
R-type
sltu rd, rs1, rs2
# Description
rd = (rs1 < rs2)?1:0
R-type
mul
# Description
rd = (rs1 * rs2)[31:0]
R-type
mulh
# Description
rd = (rs1 * rs2)[63:32]
R-type
mulsu
# Description
rd = (rs1 * rs2)[63:32]
R-type
mulu
# Description
rd = (rs1 * rs2)[63:32]
R-type
div
# Description
rd = rs1 / rs2
R-type
divu
# Description
rd = rs1 / rs2
R-type
rem
# Description
rd = rs1 % rs2
R-type
remu
# Description
rd = rs1 % rs2

I-type

I-type
addi rd, rs1, imm
# Description
rd = rs1 + imm
I-type
xori rd, rs1, imm
# Description
rd = rs1 ^ imm
I-type
ori rd, rs1, imm
# Description
rd = rs1 | imm
I-type
andi rd, rs1, imm
# Description
rd = rs1 & imm
I-type
slli rd, rs1, imm
# Description
rd = rs1 << imm[0:4]
I-type
srli rd, rs1, imm
# Description
rd = rs1 >> imm[0:4]
I-type
srai rd, rs1, imm
# Description
rd = rs1 >> imm[0:4]
I-type
slti rd, rs1, imm
# Description
rd = (rs1 < imm)?1:0
I-type
sltiu rd, rs1, imm
# Description
rd = (rs1 < imm)?1:0
I-type
lb rd, imm(rs1)
# Description
rd = M[rs1 + imm][0:7]
I-type
lh rd, imm(rs1)
# Description
rd = M[rs1 + imm][0:15]
I-type
lw rd, imm(rs1)
# Description
rd = M[rs1 + imm][0:31]
I-type
lbu rd, imm(rs1)
# Description
rd = M[rs1 + imm][0:7]
I-type
lhu rd, imm(rs1)
# Description
rd = M[rs1 + imm][0:15]
I-type
jalr rd, rs1, imm,
# Description
rd = PC + 4; PC = rs1 + imm
I-type
ecall
# Description
Transfer control to OS
I-type
ebreak
# Description
Transfer control to debugger

B-type

B-type
beq rs1, rs2, label
# Description
if(rs1 == rs2) PC += imm
B-type
bne rs1, rs2, label
# Description
if(rs1 != rs2) PC += imm
B-type
blt rs1, rs2, label
# Description
if(rs1 < rs2) PC += imm
B-type
bge rs1, rs2, label
# Description
if(rs1 >= rs2) PC += imm
B-type
bltu rs1, rs2, label
# Description
if(rs1 < rs2) PC += imm
B-type
bgeu rs1, rs2, label
# Description
if(rs1 >= rs2) PC += imm

U-type

U-type
lui rd, upimm
# Description
rd = imm << 12
U-type
auipc rd, upimm
# Description
rd = PC + (imm << 12)

J-type

J-type
jal rd, label
# Description
rd = PC + 4; PC += imm

S-type

S-type
sb rs2, imm(rs1)
# Description
M[rs1+imm][0:7] = rs2[0:7]
S-type
sh rs2, imm(rs1)
# Description
M[rs1+imm][0:15] = rs2[0:15]
S-type
sw rs2, imm(rs1)
# Description
M[rs1+imm][0:31] = rs2[0:31]
Getting Started with
0xRVENC0xRV\boxed{\text{ENC}}
A modern RISC-V instruction encoder for both single instructions and complete assembly files. Follow this guide to unlock its full potential.
01

ISA Selection

Choose your target architecture using the toggle buttons:
RV32IRV64I
02

Writing Instructions

Two ways to input your RISC-V assembly:

Direct Input

Use the built-in editor on the left with line number support for direct coding

Instruction Browser

Search and insert pre-formatted instructions from the library on the bottom right

03

Encoding Options

Choose your preferred encoding mode:

Auto-encode

Real-time encoding as you type

Manual encode

Encode on demand

04

Output Visualization

Multiple ways to view your encoded instructions:

Machine Code

0x00A02223

Binary

00000000101000000010001000100011

Interactive Diagram

Hover to explore instruction fields