tau-v2
My homebrew RISC-V microcontroller built entirely in Verilog. This is a from-scratch implementation I'm designing to learn more about CPU architecture and HDL development.
RISC-V Core
RV32I base ISA
5-stage pipeline architecture
Simulation
ModelSim testbenches
Waveform analysis
Implementation
Verilog HDL
Synthesizable design
$ cat build-notes/architecture.txt
RISC-V Implementation Details:
- RV32I base integer instruction set
- 5-stage pipeline (fetch, decode, execute, memory, writeback)
$ cat build-notes/development.txt
Development Environment:
- ModelSim for simulation and verification
- Custom testbenches for each module
- RISC-V toolchain for compiling test programs
$ cat build-notes/progress.txt
Current Progress:
- Core instruction fetch and decode working
- ALU implemented for basic arithmetic operations
- Register file completed and verified
- Still working on control logic and memory interface
$ cat build-notes/next-steps.txt
Next Steps:
- Finish implementing all RV32I instructions
- Add branch prediction logic
- Implement memory controller
- Eventually synthesize to an FPGA
Learning Experience
This project has been challenging but rewarding. I've had to rewrite the pipeline logic several times as I learned more about timing issues.
Simulation Results
ModelSim has been essential for debugging. I've written a basic test program that executes a few instructions to verify correct behavior of the ALU and register file.
Future Plans
Once I have the core working, I want to add peripherals like UART and GPIO. The end goal is to synthesize this onto an FPGA and run real programs on hardware I designed.